Features

• Core
  • 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline 
  • extended instruction set 
• Memories
  • program memory: up to 32 Kbyte Flash; data retention 20 years at 55 °C after 10 kcycle 
  • data memory: up to 1 Kbyte true data EEPROM; endurance 300 kcycle 
  • RAM: up to 2 Kbyte
• Clock, reset and supply management
  • 2.95 to 5.5 V operating voltage 
  • flexible clock control, 4 master clock sources
    • low power crystal resonator oscillator 
    • external clock input 
    • internal, user-trimmable 16 MHz RC 
    • internal low-power 128 kHz RC
  • clock security system with clock monitor 
  • power management: 
    • low-power modes (wait, active-halt, halt) 
    • switch-off peripheral clocks individually 
  • permanently active, low-consumption poweron and power-down reset
• Interrupt management
  • nested interrupt controller with 32 interrupts 
  • up to 37 external interrupts on 6 vectors 
• Timers
  • advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization 
  • 2x16-bit general purpose timer, with 2+3 CAPCOM channels (IC, OC or PWM) 
  • 8-bit basic timer with 8-bit prescaler 
  • auto wake-up timer 
  • window watchdog and independent watchdog timers 
• Communication interfaces
  • UART with clock output for synchronous operation, SmartCard, IrDA, LIN master mode 
  • SPI interface up to 8 Mbit/s 
  • I2C interface up to 400 kbit/s 
• Analog to digital converter (ADC)
  • 10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog 
• I/Os
  • up to 38 I/Os on a 48-pin package including 16 high sink outputs 
  • highly robust I/O design, immune against current injection 
• Unique ID
  • 96-bit unique key for each device