Features:

• Core
  • ARM926EJ-S™ ARM® Thumb® Processor running at up to 400 MHz @ 1.0V +/- 10%
  • 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
• Memories
  • One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, SDCard, DataFlash or serial DataFlash. Programmable order.
  • One 32-Kbyte internal SRAM, single-cycle access at system speed
  • High Bandwidth Multi-port DDR SDR SDRAM Controller (DDRSDRC)
  • 32-bit External Bus Interface supporting 4-bank and 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories
  • MLC/SLC 8-bit NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC)
• System running at up to 133 MHz
  • Power-on Reset Cells, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer and Real Time Clock
  • Boot Mode Select Option, Remap Command
  • Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
  • Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
  • One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
  • Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
  • Dual Peripheral Bridge with dedicated programmable clock for best performances
  • Two dual port 8-channel DMA Controllers (DMAC)
  • Advanced Interrupt Controller (AIC) and Debug Unit (DBGU)
  • Two Programmable External Clock Signals
• Low Power Mode
  • Shutdown Controller with four 32-bit Battery Backup Registers
  • Clock Generator and Power Management Controller
  • Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
• Peripherals
  • LCD Controller (LCDC) with overlay, alpha-blending, rotation, scaling and color conversion
  • USB Device High Speed, USB Host High Speed and USB Host Full Speed with dedicated On-Chip Transceiver
  • One 10/100 Mbps Ethernet MAC Controller (EMAC)
  • Two High Speed Memory Card Hosts
  • Two Master/Slave Serial Peripheral Interfaces (SPI)
  • Two 3-channel 32-bit Timer/Counters (TC)
  • One Synchronous Serial Controller (SSC)
  • One 4-channel 16-bit PWM Controller
  • 3 Two-wire Interfaces (TWI)
  • Three USARTs, two UARTs, one DBGU
  • One 12-channel 10-bit Touchscreen Analog-to-Digital Converter
  • Software Modem Device (SMD)
  • Write Protected Registers
• I/O
  • Four 32-bit Parallel Input/Output Controllers
  • 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
  • Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
  • Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output
• Package
  • 217-ball BGA, pitch 0.8 mm