Features:

• JEDEC Standard 204-pin Dual In-Line Memory Module
• Intend for PC3-8500 applications 
• Inputs and Outputs are SSTL-15 compatible
• VDD=VDDQ= 1.35 Volt (+0.1/-0.067)
• Bi-directional Differential Data Strobe
• DLL aligns DQ and DQS transition with CK transition
• SDRAMs have 8 internal banks for concurrent operation
• Normal and Dynamic On-Die Termination support.
• SDRAMs are 78-ball BGA Package
• 8 bit pre-fetch
• Two different termination values (Rtt_Nom & Rtt_WR)
• Auto & self refresh 7.8µs (TA ≤ +85°C)
• 15/10/1 Addressing (row/column/rank)-2GB
• DRAM operating temperature range 0°C ≤ TA ≤ +85°C
• Programmable Device Operation:
  • Burst Type: Sequential or Interleave
  • Device CAS# Latency: 7
  • Burst Length: switch on-the-fly: BL=8 or BC 4
• RoHS Compliant